20 20 100 40 Page 1 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 2 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 660 320 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 3 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 720 20 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 780 20 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 4 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 720 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 780 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 860 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 5 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 720 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 800 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 880 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 960 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 false 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 6 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 1200 340 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 700 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 760 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 820 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 880 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 940 40 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 7 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 1200 400 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 160 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 8 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1200 520 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 160 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 false 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 800 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 20 20 100 40 Page 9 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 1200 580 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 1200 640 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 220 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 300 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 740 20 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 820 20 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 10 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 1200 460 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 740 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 800 20 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 880 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 180 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 260 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 11 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 140 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 200 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31 260 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 320 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 380 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 440 0 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 false 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 20 20 100 40 Page 12 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 540 20 150 40 画面监控软件 Arial,16,-1,5,50,0,0,0,0,0 #a0a0a4 #00000000 true #a0a0a4 1 20 80 600 300 #00000000 true #a0a0a4 1 60 90 30 40 5 10 50 200 #c0c0c0 -50 1000 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 60 1 #00ffff #ffff00 #ff00ff #00ff00 曲线1 曲线2 曲线3 曲线4 IASC2_CHS_ARINC_OUT_L231_CH_FAULT IASC2B_ARINC_OUT_L260_TAV2_OPEN IASC2A_ARINC_OUT_L270_CABIN_NEG_DIFF_PRESS_W IASC1B_ARINC_OUT_L270_CABIN_HI_DIFF_PRESS_W 660 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 -150 240 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2B_ARINC_OUT_L270_HAAO_MODE_ON 900 120 200 200 [0, 20) [20, 40) [40, 60) [60, 80) [80, 100] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 0 100 5 10 0 270 1 1 true 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 #ffffff SimSun,9,-1,5,50,0,0,0,0,0 #c0c0c0 true IASC2A_ARINC_OUT_L272_FCV_FAIL_IN_POSITION 1120 20 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 4 IASC2B_ARINC_OUT_L272_PACK_DEGRADED 1120 80 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 3 IASC1A_ARINC_OUT_L272_TRIM_AIR_DEGRADED 1120 140 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 2 IASC2B_ARINC_OUT_L272_TRIM_AIR_OFF 1120 200 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 1 IASC2B_ARINC_OUT_L272_TAPRV_OPEN 1120 260 135 40 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true 2 Arial,16,-1,5,50,0,0,0,0,0 0 IASC2A_ARINC_OUT_L304_PACK_CLOSE_CMD 20 400 300 300 #00000000 true #a0a0a4 1 #a0a0a4 SimSun,9,-1,5,50,0,0,0,0,0 20 -5 5 -5 5 1 1 1 true true #ff0000 #00ff00 左 右 20 16 1 2 3 5 IASC2A_ARINC_OUT_L306_FWD_EFAN_SPEED_CMD LRM_B1_L345_R_Lane1_Shield6_Failed_Shorted LRM_B1_L344_L_Lane2_Shield6_Failed_Open LRM_A1_L347_L_FRDC_CH_A_CANbus_Fault 560 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical HM_R1_RDIU_07_Status_RDIU_RTD_PT500_01_Validity_Fault 780 400 200 200 [0, 100) [100, 200) [200, 300) [300, 400) [400, 500] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 140 #00000000 true #a0a0a4 1 true 20 2 10 4 SimSun,9,-1,5,50,0,0,0,0,0 SimSun,9,-1,5,50,0,0,0,0,0 1 1 Vertical EPS1_L_BPCU_LTRU_VOLT 1000 400 200 200 [-10, -5) [-5, 0) [0, 20] (20, 25] (25, 30] #ff0000 #ffff00 #00ff00 #ffff00 #ff0000 #ffffff 0 #00000000 true #a0a0a4 1 -10 30 5 10 SimSum,10,-1,5,50,0,0,0,0,0 1 20 Vertical FCM_1_429_IDU_LI_LO_L204_SSM_FCM1 360 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_005_wd_08_spare_3D84_17_27_27 440 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ssu_capt_ap_det_sov_tst_flt_set_3D65 520 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 sp_op_xch_1_010_wd_01_spare_2D83_3_25_25 600 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 ail_rib_adb_health_mon_tst_maint_rst_2D65 680 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 mfs_5l_reu_flt_rst_2D65 340 400 200 200 #00000000 true #a0a0a4 1 20 -2 2 -2 2 1 1 1 #00ff00 #00ff00 SimSun,9,-1,5,50,0,0,0,0,0 5 true 1000 #ff00ff #00ffff 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LRM_A1_L344_L_Lane2_Shield6_Failed_Open FADEC_L_CHB_PHM_Maintenance_Word_9_Fault_Repot_021 760 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 AOA1_L1_SIN_4D30 840 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 RUD_LWR_ENGAGE_EHSV_HI_CMD_WA_REU_7D44 920 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 elev_l_rig_positive_flt_set_1D65 1000 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_005_wd_21_spare_1D65_44_8_8 1080 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 irs_1_ir_vert_accel_comp_fl_1D84 1140 620 60 60 [0, 1) [1, 2) [2, 3) [3, 4) [4, 5) #00ff00 #ffff00 #808000 #ff0000 #800000 #ffffff 0 pf_op_xch_1_040_wd_10_spare_2D62_21_0_31